1. Field of the Invention
The present invention relates to a semiconductor device including a plurality of elements which have different electrical characteristics and a method for manufacturing the semiconductor device.
2. Description of the Background Art
To form a plurality of elements having different electrical characteristics on a semiconductor substrate, in general, it is necessary to divide the semiconductor substrate into regions by characteristics of the elements and form the elements under different conditions on a region-by-region basis. In a logic mixed memory where a logic circuit and a memory circuit are formed together in a chip, especially, the elements should be formed with care. That is because oxide films of different thicknesses have to be formed on a substrate. Specifically, a MOS transistor in a logic circuit uses a thin gate oxide film for faster operation while a MOS transistor in a DRAM memory cell circuit uses a thicker gate oxide film than that in the logic circuit since it has to ensure reliability of oxide film because of operation with high voltage across a word line.
FIG. 9 is a cross section illustrating a structure of a logic mixed memory. This figure partly shows a memory circuit region 4 and a logic circuit region 5 on a semiconductor substrate 1 and in each of the regions, some elements are provided being isolated by isolation regions 20. A transistor 9 is provided with a source/drain region 17, a gate electrode 15D, a gate oxide film 7 and a side-wall oxide film 16, and a transistor 10 is provided with the source/drain region 17, a gate electrode 15E, a gate oxide film 8 and the side-wall oxide film 16. The gate oxide film 8 of the transistor 10 in the memory circuit region 4 is thick and the gate oxide film 7 of the transistor 9 in the logic circuit region 5 is thin.
In short, to form the logic mixed memory, a technique of forming a plurality of MOS transistors having oxide films of different thicknesses on a substrate is needed. As such a technique, there is a method where a thin oxide film is formed by oxidizing uniformly on the whole surface of a wafer, the oxide film on a memory circuit region is removed by etching with a logic circuit region masked and thereafter a thick oxide film is formed by oxidizing the memory circuit region of the wafer again. Or, conversely, a method where a thick oxide film is formed first and then a thin oxide film is formed is shown in Japanese Patent Application Laid Open Gazette 10-22397, for example.
With size reduction of semiconductor device, it is becoming indispensable to use a trench isolation in forming a device, for efficient isolation of elements constituting the device. The trench isolation refers to a method for electrical isolation of elements, where a trench is formed in a substrate by anisotropic etching and filled with an insulating film by CVD and the like and planarization is performed on its surface. The trench isolation has an advantage of forming a narrow and deep isolation region since it hardly causes bird""s beak which would be caused by a prior-art isolation method, LOCOS. The logic mixed memory also needs the trench isolation.
In general, to enhance integration in the memory circuit region, it is necessary to reduce a trench region as well as an active region in which elements exist. Therefore, the trench in the memory circuit region is formed narrower than that in the logic circuit region. FIG. 10 is a cross section showing only trenches with transistors omitted. A trench 2 in the memory circuit region 4 is narrower than a trench 200 in the logic circuit region 5. The trench 200 in the logic circuit region 5 typically has a width of about 0.28 xcexcm and the trench 2 in the memory circuit region 4 typically has a width of about 0.24 xcexcm, though the widths vary depending on manufacturing method, device and the like. Naturally, trenches of various widths are formed in a circuit.
Oxides 3A and 3B are provided in the trenches 200 and 2, respectively. On a surface of the oxide 3B filling the trench 2 in the memory circuit region 4, a pothole 6 called xe2x80x9cseamxe2x80x9d is created. The following discussion will be made on the cause of creation of the seam 6. Using the CVD make it hard to supply a gas in a very small region. When the oxide 3 is gradually deposited in the trench 2 by CVD inwardly from an inwall of the narrow trench 2, a portion where no oxide 3 is deposited is likely to exist in the center of the trench 2. In some cases, there is a void inside the trench 2. This has an influence on a portion of the oxide deposited above the uppermost surface of the trench, to create a V-shaped pothole thereon. Further, after removing the oxide 3 deposited above the uppermost surface of the trench by etch-back treatment, CMP or the like to perform planarization on the surface, the seam 6 is likely to exist in the center of the trench as shown in FIG. 10. That is because the etching and the like proceed faster and the remaining void is likely to show up in the center of trench due to little oxide 3 deposited therein. The creation of the seam 6 becomes pronounced in particular when the trench has a width of 0.2 xcexcm or less.
That is the cause of creation of the seam. The next discussion will be made on a problem caused by existence of the seam 6. For example, when a polysilicon is formed uniformly on a surface of the substrate in the memory circuit region 4 of FIG. 10 and thereafter an unnecessary portion is etched, with a necessary portion left on a predetermined surface other than the trench 2, to form a gate electrode, if the seam 6 exists, the polysilicon is likely to remain in the seam 6. The trench 2 extends perpendicular to the sheet of FIG. 10 and the remaining polysilicon linearly exists in this direction.
Through several steps after that, the MOS transistor structure 10 is formed as shown in FIG. 11. FIG. 12 illustrates the MOS transistor structure 10 viewed from the upper side, i.e., from the direction of the arrow (FIG. 11 is a cross section taken along the line of XIxe2x80x94XI of FIG. 12). In FIG. 12, the polysilicon 15E serving as a gate electrode is formed across the trench 2 for the convenience of interconnection. When the polysilicon 15E remains in the seam 6 existing in the trench 2, if another gate electrode material (not shown in FIG. 12), for example, exists across the trench 2, a short circuit occurs between the gate electrode material and the polysilicon gate electrode 15E, causing a hindrance in the circuit.
That is the problem caused by existence of the seam. Various measures against the creation of the seam have been considered. For example, Japanese Patent Application Laid Open Gazette 7-326659 discloses a technique of filling a trench with an oxide in two stages. In the first stage, the first oxide film is deposited up to above a surface of a trench. In the subsequent stage, an etching is performed to the extent that the oxide inside the trench should be slightly removed and left to some extent, and the second oxide film is deposited thereon up to above the surface of the trench and thereafter etched for planarization of the surface.
In consideration of the above prior art, to provide a logic mixed memory in which trench isolation regions of different widths and oxide films of different thicknesses are formed in a semiconductor substrate, it is necessary to execute a step for coping with the seam on the trench isolation region and thereafter execute a step of forming the oxide films of different thicknesses. When the prior art is simply used, the method needs increased number of steps even becomes inefficient and costly due to repeating steps of forming and removing the oxide films.
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: a semiconductor substrate having a surface; a trench having an opening in the surface of the semiconductor substrate; a first insulator provided inside the trench; a conductor existing on a surface of the first insulator opposed to the opening; and a second insulator covering at least the conductor.
According to a second aspect of the present invention, the semiconductor device of the first aspect further comprises: a third insulator provided on the surface of the semiconductor substrate, the second insulator is provided also on the third insulator, and the semiconductor device further comprises: a first MOS element having the third insulator as a gate insulating film and isolated from an adjacent first MOS element by the trench; and a second MOS element having the second and third insulators as a gate insulating film and isolated from an adjacent second MOS element by the trench.
The present invention is also directed to a method for manufacturing a semiconductor device. According to a third aspect of the present invention, the method comprises the steps of: (a) forming a trench inside a semiconductor substrate having a surface divided into first and second regions to have an opening in the surface and forming a first insulator inside the trench; (b) forming a second insulator in a portion of the surface where no opening of the trench is provided; (c) forming a conductor on the whole surface of a structure obtained by the steps (a) and (b); (d) removing the conductor in the first region to expose the second insulator; and (e) forming a third insulator on the whole surface of at least the first region in the structure obtained by the steps (a) and (b).
According to a fourth aspect of the present invention, in the method of the third aspect, the conductor existing on a surface of the first insulator opposed to the opening is left in the step (d).
According to a fifth aspect of the present invention, in the method of the third or fourth aspect, the trench in the first region is narrower than that in the second region.
In the semiconductor device in accordance with the first aspect of the present invention, if the conductor exists on the first insulator in the trench, the second insulator avoids a short circuit between the conductor and other interconnect lines.
In the semiconductor device of the second aspect of the present invention, since the gate insulating film of the first MOS element is thinner than that of the second MOS element, the first MOS element is used in the logic circuit to achieve a faster operation and the second MOS element is used in the memory circuit to achieve a high breakdown-voltage operation, for example, and thus both the first and second MOS elements can be formed on a semiconductor substrate.
In the method for manufacturing a semiconductor device of the third aspect of the present invention, it becomes easier to form the MOS element with a thick gate insulating film consisting of the second and third insulators in the first region and the MOS element with a thin gate insulating film made of the second insulator in the second region. Moreover, when the conductor is not completely removed in the step (d), the first and third insulators isolate the remaining conductor from the surrounding elements, to avoid an unnecessary short circuit.
In the method of the fourth aspect of the present invention, if the flatness of the first insulator is deteriorated, the conductor remaining at the opening of the trench improves the flatness, thereby making it easier to form the third insulator.
In the method of the fifth aspect of the present invention, since the third insulator covers the conductor in the narrower trench, remarkable effects of the third and fourth aspects can be achieved in a trench where the flatness of the first insulator is likely to deteriorate and the conductor is likely to remain in the step (d).
An object of the present invention is to provide a semiconductor device in which trench isolation regions of different widths and oxide films of different thicknesses are formed and the oxide films serve to cope with seams created in surfaces of the trench isolation regions, and to provide a method for manufacturing the semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.